2784 search results - page 18 / 557 » Instruction Level Parallelism |
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
ICPP
2009
IEEE
13 years 7 months ago
2009
IEEE
Several multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is ...
CASES
2001
ACM
14 years 1 months ago
2001
ACM
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
MICRO
1993
IEEE
14 years 1 months ago
1993
IEEE
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...
CF
2006
ACM
14 years 3 months ago
2006
ACM
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...