2784 search results - page 19 / 557 » Instruction Level Parallelism |
IPPS
1997
IEEE
14 years 2 months ago
1997
IEEE
The large design space of modern computer architectures calls for performance modelling tools to facilitate the evaluation of different alternatives. In this paper, we give an ove...
ISPAN
2000
IEEE
14 years 2 months ago
2000
IEEE
In this paper, we evaluate a mechanism to reissue instructions on the mispredicted speculation path. An instruction which is once dispatched to a functional unit during mispredict...
ISPASS
2010
IEEE
14 years 4 months ago
2010
IEEE
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
PPOPP
2006
ACM
14 years 3 months ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
ISCA
2010
IEEE
13 years 8 months ago
2010
IEEE
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...