2784 search results - page 26 / 557 » Instruction Level Parallelism |
HPCA
2006
IEEE
14 years 10 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
HPCA
2004
IEEE
14 years 10 months ago
2004
IEEE
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
MEMICS
2010
13 years 4 months ago
2010
We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer leve...
MICRO
1997
IEEE
14 years 1 months ago
1997
IEEE
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
ACL
2010
13 years 8 months ago
2010
In this paper, we address the task of mapping high-level instructions to sequences of commands in an external environment. Processing these instructions is challenging--they posit...