2784 search results - page 27 / 557 » Instruction Level Parallelism |
VLSID
2008
IEEE
14 years 10 months ago
2008
IEEE
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
LCTRTS
1998
Springer
14 years 2 months ago
1998
Springer
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
DSN
2006
IEEE
14 years 3 months ago
2006
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
LCTRTS
2001
Springer
14 years 2 months ago
2001
Springer
