2784 search results - page 29 / 557 » Instruction Level Parallelism |
APCCAS
2002
IEEE
14 years 2 months ago
2002
IEEE
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the sw...
EUROPAR
2000
Springer
14 years 1 months ago
2000
Springer
This paper investigates the potential for automatic mapping of typical embedded applications to architectures with multimedia instruction set extensions. For this purpose a (patter...
ESTIMEDIA
2007
Springer
14 years 4 months ago
2007
Springer
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
Information about instruction criticality can be used to control the application of micro-architectural resources efficiently. To this end, several groups have proposed methods t...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...