2784 search results - page 37 / 557 » Instruction Level Parallelism |
ICCD
2002
IEEE
14 years 6 months ago
2002
IEEE
Subword parallelism has succeeded in accelerating many multimedia applications. Subword permutation instructions have been proposed to efficiently rearrange subwords in or among r...
HPCA
1999
IEEE
14 years 2 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
HPCA
2001
IEEE
14 years 10 months ago
2001
IEEE
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
EUROMICRO
1997
IEEE
14 years 2 months ago
1997
IEEE
CMOS technology should, over the next few years, reach lithography of under 0.1¡ . This provides a die area improvement of a factor of 10 over today’s technology. What is the b...
ACSC
2004
IEEE
14 years 1 months ago
2004
IEEE
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...