2784 search results - page 44 / 557 » Instruction Level Parallelism |
HPCA
1995
IEEE
14 years 1 months ago
1995
IEEE
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
VLSISP
2008
13 years 9 months ago
2008
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
SAMOS
2004
Springer
14 years 3 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...