2784 search results - page 4 / 557 » Instruction Level Parallelism |
ASPLOS
1989
ACM
14 years 1 months ago
1989
ACM
ISCA
1998
IEEE
14 years 2 months ago
1998
IEEE
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
MICRO
1992
IEEE
14 years 1 months ago
1992
IEEE
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
HIPC
2000
Springer
14 years 1 months ago
2000
Springer
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
ICPP
1999
IEEE
14 years 2 months ago
1999
IEEE
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...