2784 search results - page 54 / 557 » Instruction Level Parallelism |
ISHPC
2003
Springer
14 years 3 months ago
2003
Springer
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hard...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...
HICSS
1994
IEEE
14 years 2 months ago
1994
IEEE
Our research goal is to design systems that enable humans to teach tedious, repetitive, simple tasks to a computer. We propose here a learner/problem solver architecture for such ...
CATA
2004
13 years 11 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
ICPP
2000
IEEE
14 years 2 months ago
2000
IEEE
This work considers the use of a n S M T (simultaneous multithreading) processor in lieu of the conventional processor(s) in a router and evaluates quantitatively the potential ga...