2784 search results - page 56 / 557 » Instruction Level Parallelism |
ISQED
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the l...
IEEEPACT
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
ISCA
1989
IEEE
14 years 2 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
IPPS
2005
IEEE
14 years 3 months ago
2005
IEEE
We study the energy efficiency benefits of bypassing trivial computations in high-performance processors. Trivial computations are those computations whose output can be determine...