2784 search results - page 61 / 557 » Instruction Level Parallelism |
PLDI
1996
ACM
14 years 2 months ago
1996
ACM
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this pape...
CASES
2007
ACM
14 years 1 months ago
2007
ACM
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...
IFIP
1993
Springer
14 years 2 months ago
1993
Springer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
ICVGIP
2008
13 years 11 months ago
2008
Usage of statistical classifiers, namely AdaBoost and its modifications, in object detection and pattern recognition is a contemporary and popular trend. The computatiponal perfor...
ICPP
1999
IEEE
14 years 2 months ago
1999
IEEE
Instruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars. In this paper, we focus on Database applicatio...