91 search results - page 16 / 19 » Instruction Selection for Compilers that Target Architecture... |
SAMOS
2005
Springer
14 years 1 months ago
2005
Springer
—We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor. The processor model is described using the Sandblaster architect...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
IEEEPACT
2002
IEEE
14 years 16 days ago
2002
IEEE
Having a representative workload of the target domain of a microprocessor is extremely important throughout its design. The composition of a workload involves two issues: (i) whic...
WCRE
2002
IEEE
14 years 15 days ago
2002
IEEE
The University of Queensland Binary Translator (UQBT ) is a static binary translation framework that allows for the translation of binary, executable programs, from one architectu...
HPCA
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...