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ISCA
2009
IEEE
138views Hardware» more  ISCA 2009»
14 years 1 months ago
Achieving predictable performance through better memory controller placement in many-core CMPs
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
Dennis Abts, Natalie D. Enright Jerger, John Kim, ...
ECBS
2003
IEEE
111views Hardware» more  ECBS 2003»
14 years 7 days ago
Multigranular Simulation of Heterogeneous Embedded Systems
Heterogeneous embedded systems, where configurable or application specific hardware devices (FPGAs and ASICs) are used alongside traditional processors, are becoming more and more...
Aditya Agrawal, Ákos Lédeczi
CASES
2006
ACM
14 years 27 days ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
DAC
2008
ACM
14 years 8 months ago
Daedalus: toward composable multimedia MP-SoC design
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
Hristo Nikolov, Mark Thompson, Todor Stefanov, And...
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 8 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...