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136
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CF
2004
ACM
15 years 9 months ago
Integrated temporal and spatial scheduling for extended operand clustered VLIW processors
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
Rahul Nagpal, Y. N. Srikant
141
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VISUALIZATION
1995
IEEE
15 years 7 months ago
An Integrated Approach for Steering, Visualization, and Analysis of Atmospheric Simulations
In the research described here, we have constructed at tightly coupled set of methods for monitoring, steering, and applying visual analysis to large scale simulations. This work ...
Yves Jean, Thomas Kindler, William Ribarsky, Weimi...
121
Voted
APPINF
2003
15 years 5 months ago
Hardware Impact on Communication Performance of Beowulf LINUX Cluster
There exist a lot of models of parallel computation, amongst which LogP and LogGP are famous and suitable to describe the framework of communication process of Beowulf LINUX Clust...
Yuan Tang, Yun-Quan Zhang, Jia-Chang Sun, Yu-Cheng...
112
Voted
ICPP
2005
IEEE
15 years 9 months ago
Automatic Experimental Analysis of Communication Patterns in Virtual Topologies
Automatic pattern search in event traces is a powerful method to identify performance problems in parallel applications. We demonstrate that knowledge about the virtual topology, ...
Nikhil Bhatia, Fengguang Song, Felix Wolf, Jack Do...
138
Voted
HPCA
2008
IEEE
16 years 4 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...