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» Integrating Temporal Logics
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DAC
2005
ACM
14 years 8 months ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu
DAC
2006
ACM
14 years 8 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
DAC
2006
ACM
14 years 8 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan
DAC
2006
ACM
14 years 8 months ago
An adaptive FPGA architecture with process variation compensation and reduced leakage
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
Georges Nabaa, Navid Azizi, Farid N. Najm
SIGSOFT
2007
ACM
14 years 8 months ago
On marrying ontological and metamodeling technical spaces
In software engineering, the use of models and metamodeling approaches (e.g., MDA with MOF/UML) for purposes such as software design or software validation is an established pract...
Fernando Silva Parreiras, Steffen Staab, Andreas W...