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» Integrative Levels of Program Comprehension
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DAC
2007
ACM
14 years 8 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
PPOPP
2009
ACM
14 years 2 months ago
NePalTM: design and implementation of nested parallelism for transactional memory systems
Abstract. Transactional memory (TM) promises to simplify construction of parallel applications by allowing programmers to reason about interactions between concurrently executing c...
Haris Volos, Adam Welc, Ali-Reza Adl-Tabatabai, Ta...
GLOBECOM
2009
IEEE
14 years 2 months ago
LA-MAC: A Load Adaptive MAC Protocol for MANETs
—The performance of prevalent MAC protocols in MANETs relies on the level of contention in networks. While contention-based MAC protocols such as CSMA suffer from inefficiency u...
Weihong Hu, Xiaolong Li, Homayoun Yousefi'zadeh
DSN
2008
IEEE
14 years 1 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 1 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...