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HIPEAC
2010
Springer
14 years 7 months ago
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors
Abstract. The shared-cache contention on Chip Multiprocessors causes performance degradation to applications and hurts system fairness. Many previously proposed solutions schedule ...
Yunlian Jiang, Kai Tian, Xipeng Shen
RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
14 years 4 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
ICRA
2009
IEEE
145views Robotics» more  ICRA 2009»
14 years 4 months ago
A two-steps next-best-view algorithm for autonomous 3D object modeling by a humanoid robot
— A novel approach is presented which aims at building autonomously visual models of unknown objects, using a humanoid robot. Although good methods have been proposed for the spe...
Torea Foissotte, Olivier Stasse, Adrien Escande, P...
DATE
2008
IEEE
85views Hardware» more  DATE 2008»
14 years 4 months ago
Video Processing Requirements on SoC Infrastructures
Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large sto...
Pieter van der Wolf, Tomas Henriksson
DFT
2007
IEEE
103views VLSI» more  DFT 2007»
14 years 4 months ago
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
Avijit Dutta, Nur A. Touba