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CODES
2004
IEEE
14 years 1 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
CHES
2006
Springer
179views Cryptology» more  CHES 2006»
14 years 1 months ago
Offline Hardware/Software Authentication for Reconfigurable Platforms
Abstract. Many Field-Programmable Gate Array (FPGA) based systems utilize third-party intellectual property (IP) in their development. When they are deployed in non-networked envir...
Eric Simpson, Patrick Schaumont
ENGL
2008
100views more  ENGL 2008»
13 years 9 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid
AINA
2010
IEEE
13 years 6 months ago
Neural Network Trainer through Computer Networks
- This paper introduces a neural network training tool through computer networks. The following algorithms, such as neuron by neuron (NBN) [1][2], error back propagation (EBP), Lev...
Nam Pham, Hao Yu, Bogdan M. Wilamowski
CCS
2011
ACM
12 years 9 months ago
On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs
Over the last two decades FPGAs have become central components for many advanced digital systems, e.g., video signal processing, network routers, data acquisition and military sys...
Amir Moradi, Alessandro Barenghi, Timo Kasper, Chr...