We propose the notion of logical reliability for real-time program tasks that interact through periodically updated program variables. We describe a reliability analysis that chec...
Krishnendu Chatterjee, Arkadeb Ghosal, Thomas A. H...
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
A system based on a hierarchical scheduler is a system in which the processor is shared between several collaborative schedulers. Such schedulers exist since 1960 and they are bec...