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DATE
2009
IEEE
93views Hardware» more  DATE 2009»
15 years 11 months ago
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Ha...
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
15 years 11 months ago
A link arbitration scheme for quality of service in a latency-optimized network-on-chip
Abstract—Networks-on-chip (NoC) for general-purpose multiprocessors require quality of service mechanisms to allow realtime streaming applications to be executed along with laten...
Jonas Diemer, Rolf Ernst
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
15 years 11 months ago
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
Abstract—Complex software programs are mostly characterized by phase behavior and runtime distributions. Due to the dynamism of the two characteristics, it is not efficient to m...
Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
15 years 11 months ago
An event-guided approach to reducing voltage noise in processors
Abstract—Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage “emergency”, i.e., a swing beyond tol...
Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. H...
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
15 years 11 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
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