Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing

Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed Test Point Insertion technique in terms of timing, area and power.

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod
• Keywords: DATE 2009, Defect Coverage, Hardware, Reduction Design Technique, Voltage Settings