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» Interblock memory for turbo coding
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TCOM
2010
77views more  TCOM 2010»
13 years 9 months ago
Interblock memory for turbo coding
—We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achie...
Chia-Jung Yeh, Yeong-Luh Ueng, Mao-Chao Lin, Ming-...
ISCAS
2007
IEEE
109views Hardware» more  ISCAS 2007»
14 years 5 months ago
Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding
—This paper presents an energy-efficient turbo decoder based on border metric encoding, which is especially suitable for non-binary circular turbo codes. In the proposed method, ...
Ji-Hoon Kim, In-Cheol Park
ISCAS
2008
IEEE
111views Hardware» more  ISCAS 2008»
14 years 5 months ago
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
—Convolutional turbo decoding requires large data access and consumes large memories. To reduce the size of the metrics memory, the traceback MAP decoding is introduced for doubl...
Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu
ETT
2000
106views Education» more  ETT 2000»
13 years 10 months ago
On Union Bounds for Random Serially Concatenated Turbo Codes with Maximum Likelihood Decoding
The input-output weight enumeration (distribution) function of the ensemble of serially concatenated turbo codes is derived, where the ensemble is generated by a uniform choice ov...
Igal Sason, Shlomo Shamai
ICC
2007
IEEE
147views Communications» more  ICC 2007»
14 years 5 months ago
VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Moha...