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ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 7 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 10 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong
IPPS
2005
IEEE
14 years 4 months ago
A Cellular Multi-Objective Genetic Algorithm for Optimal Broadcasting Strategy in Metropolitan MANETs
Mobile Ad-hoc Networks (MANETs) are composed of a set of communicating devices which are able to spontaneously interconnect without any pre-existing infrastructure. In such scenar...
Enrique Alba, Bernabé Dorronsoro, Francisco...
ISJGP
2010
13 years 7 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 10 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng