154 search results - page 19 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
ISVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
FPL
2009
Springer
14 years 3 months ago
2009
Springer
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
ICCAD
2007
IEEE
14 years 7 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
ISPD
2012
ACM
12 years 6 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
GLVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...