154 search results - page 21 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
CF
2007
ACM
14 years 2 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
SLIP
2005
ACM
14 years 4 months ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
FCCM
2008
IEEE
14 years 4 months ago
2008
IEEE
With a multitude of technological innovations, one emerging trend in image processing, and medical image processing, in particular, is custom hardware implementation of computatio...
TCAD
2002
13 years 10 months ago
2002
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...