154 search results - page 28 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
IPPS
2002
IEEE
14 years 3 months ago
2002
IEEE
Modern high speed interconnects such as Myrinet and Gigabit Ethernet have shifted the bottleneck in communication from the interconnect to the messaging software at the sending an...
ISPD
2003
ACM
14 years 3 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
ISVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ISCA
2008
IEEE
13 years 10 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
ANCS
2011
ACM
12 years 10 months ago
2011
ACM
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...