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» Interconnect design methods for memory design
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IWSOC
2003
IEEE
97views Hardware» more  IWSOC 2003»
14 years 29 days ago
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compressi...
Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio...
ISSS
2000
IEEE
128views Hardware» more  ISSS 2000»
14 years 2 days ago
Hardware Synthesis from SPDF Representation for Multimedia Applications
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
Chanik Park, Soonhoi Ha
EUROGP
2000
Springer
177views Optimization» more  EUROGP 2000»
13 years 11 months ago
Register Based Genetic Programming on FPGA Computing Platforms
The use of FPGA based custom computing platforms is proposed for implementing linearly structured Genetic Programs. Such a context enables consideration of micro architectural and ...
Malcolm I. Heywood, A. Nur Zincir-Heywood
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 2 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
SIGMETRICS
2002
ACM
104views Hardware» more  SIGMETRICS 2002»
13 years 7 months ago
Improving cluster availability using workstation validation
We demonstrate a framework for improving the availability of cluster based Internet services. Our approach models Internet services as a collection of interconnected components, e...
Taliver Heath, Richard P. Martin, Thu D. Nguyen