Hardware Synthesis from SPDF Representation for Multimedia Applications

Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multimedia applications since they do not support global parameter update. In this paper, we propose a VHDL code generation method from synchronous piggybacked dataflow (SPDF) which is an extension of synchronous dataflow (SDF) for representing multimedia applications. Through constructing globally shared memory structure with limited access, we can obtain an efficient RTL architecture in terms of memory and performance compared with other approaches. We demonstrate the usefulness of the proposed approach using a preliminary example of MP3 decoders.

• Type: Conference
• Year: 2000
• Where: ISSS
• Authors: Chanik Park, Soonhoi Ha
• Keywords: Dataflow, Hardware, ISSS 2000, Synchronous Dataflow, Synchronous Piggybacked Dataflow