816 search results - page 110 / 164 » Interconnect design methods for memory design |
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
DSD
2006
IEEE
14 years 1 months ago
2006
IEEE
Traditionally, an embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems difficult for many companies, a...
ISVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
CDC
2009
IEEE
14 years 12 days ago
2009
IEEE
— This paper deals with the class of polynomially uncertain continuous-time linear time-invariant (LTI) systems whose uncertainties belong to a semi-algebraic set. The objective ...