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» Interconnect design methods for memory design
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FPL
2005
Springer
122views Hardware» more  FPL 2005»
14 years 1 months ago
FPGA-Aware Garbage Collection in Java
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...
Philippe Faes, Mark Christiaens, Dries Buytaert, D...
ETS
2000
IEEE
154views Hardware» more  ETS 2000»
13 years 7 months ago
The Knowledge Depot: Building and Evaluating a Knowledge Management System
Organizations have long had the need to record and protect the knowledge that is their intellectual capital. However, the primary burden for knowledge management has been borne by...
Beatrix Zimmermann, Michael E. Atwood, Sabina Webb...
BMCBI
2010
139views more  BMCBI 2010»
13 years 7 months ago
A highly efficient multi-core algorithm for clustering extremely large datasets
Background: In recent years, the demand for computational power in computational biology has increased due to rapidly growing data sets from microarray and other high-throughput t...
Johann M. Kraus, Hans A. Kestler
SAC
2009
ACM
14 years 2 months ago
Impact of NVRAM write cache for file system metadata on I/O performance in embedded systems
File systems make use of part of DRAM as the buffer cache to enhance its performance in traditional systems. In this paper, we consider the use of Non-Volatile RAM (NVRAM) as a w...
In Hwan Doh, Hyo J. Lee, Young Je Moon, Eunsam Kim...
HPCA
1998
IEEE
13 years 11 months ago
The Effectiveness of SRAM Network Caches in Clustered DSMs
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...
Adrian Moga, Michel Dubois