816 search results - page 15 / 164 » Interconnect design methods for memory design |
RECOSOC
2007
13 years 9 months ago
2007
Electronic equipments with higher performance, lower power consumption, and smaller size motivate the research for more efficient design methods. Platform-based design is a method...
SBACPAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large sto...
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...