816 search results - page 20 / 164 » Interconnect design methods for memory design |
GECCO
2009
Springer
14 years 2 months ago
2009
Springer
The paper deals with optimization of collective communications on multistage interconnection networks (MINs). In the experimental work, unidirectional MINs like Omega, Butterfly a...
VLSID
2000
IEEE
13 years 12 months ago
2000
IEEE
The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— In this paper we propose a method for lowering the power consumption in our previously proposed method for approximating elementary functions. By rearranging the interconnect o...
ICRA
2003
IEEE
14 years 25 days ago
2003
IEEE
− A behavior-based control and learning architecture is proposed, where reinforcement learning is applied to learn proper associations between stimulus and response by using two ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...