816 search results - page 22 / 164 » Interconnect design methods for memory design |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
ESTIMEDIA
2007
Springer
14 years 1 months ago
2007
Springer
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes t...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- Due to photo-lithography effects and manufacture process variations, the actual features fabricated on the wafer are different from the designed ones. This difference ca...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...