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» Interconnect design methods for memory design
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GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 2 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
DFT
1997
IEEE
141views VLSI» more  DFT 1997»
13 years 12 months ago
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs
Recent increases in the density and size of memory ICs made it ne cessary to search for new defect tolerance techniques since the traditional methods are no longer e ective enough...
Israel Koren, Zahava Koren
ERSA
2010
199views Hardware» more  ERSA 2010»
13 years 5 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
JOCN
2010
70views more  JOCN 2010»
13 years 6 months ago
Optimizing Design Efficiency of Free Recall Events for fMRI
â–  Free recall is a fundamental paradigm for studying memory retrieval in the context of minimal cue support. Accordingly, free recall has been extensively studied using behavior...
Ilke Öztekin, Nicole M. Long, David Badre
IPPS
2009
IEEE
14 years 2 months ago
Validating Wrekavoc: A tool for heterogeneity emulation
Experimental validation and testing of solutions designed for heterogeneous environment is a challenging issue. Wrekavoc is a tool for performing such validation. It runs unmodiï¬...
Olivier Dubuisson, Jens Gustedt, Emmanuel Jeannot