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» Interconnect design methods for memory design
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ASPDAC
2007
ACM
106views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Bisection Based Placement for the X Architecture
Rising interconnect delay and power consumption have motivated the investigation of alternative integrated circuit routing architectures. In particular, the X Architecture, which ...
Satoshi Ono, Sameer Tilak, Patrick H. Madden
PPOPP
2006
ACM
14 years 2 months ago
Fast and transparent recovery for continuous availability of cluster-based servers
Recently there has been renewed interest in building reliable servers that support continuous application operation. Besides maintaining system state consistent after a failure, o...
Rosalia Christodoulopoulou, Kaloian Manassiev, Ang...
GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
14 years 3 months ago
A destructive evolutionary process: a pilot implementation
This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determin...
Joe Sullivan, Conor Ryan
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 3 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
14 years 3 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind