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» Interconnect design methods for memory design
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GECCO
2007
Springer
326views Optimization» more  GECCO 2007»
14 years 1 months ago
Binary differential evolution for the unit commitment problem
The Unit Commitment Problem (UCP) is the task of finding an optimal turn on and turn off schedule for a group of power generation units over a given time horizon to minimize ope...
Ali Keles
FDL
2005
IEEE
14 years 1 months ago
SystemC-WMS: A Wave Mixed Signal Simulator
This paper proposes a methodology for extending SystemC to mixed signal systems, aimed at allowing the reuse of analog models and to the simulation of heterogeneous systems. To th...
Simone Orcioni, Giorgio Biagetti, Massimo Conti
ASPDAC
1999
ACM
107views Hardware» more  ASPDAC 1999»
14 years 1 days ago
New Multilevel and Hierarchical Algorithms for Layout Density Control
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
ICCD
1996
IEEE
108views Hardware» more  ICCD 1996»
13 years 12 months ago
Module Generators for a Regular Analog Layout
In general, automatic layout composition techniques based on pre-designed devices facilitate the production of small IC numbers by prefabricating their basic structures. They also...
J. Kampe, C. Wisser, G. Scarbata
ICCAD
1995
IEEE
95views Hardware» more  ICCAD 1995»
13 years 11 months ago
A sequential quadratic programming approach to concurrent gate and wire sizing
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
Noel Menezes, Ross Baldick, Lawrence T. Pileggi