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» Interconnect design methods for memory design
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DSD
2004
IEEE
97views Hardware» more  DSD 2004»
13 years 11 months ago
Scene Management Models and Overlap Tests for Tile-Based Rendering
Tile-based rendering (also called chunk rendering or bucket rendering) is a promising technique for low-power, 3D graphics platforms. This technique decomposes a scene into smalle...
Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassil...
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 29 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
ISSS
2000
IEEE
290views Hardware» more  ISSS 2000»
14 years 2 days ago
Mapping Array Communication onto FIFO Communication - Towards an Implementation
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...
Jeffrey Kang, Albert van der Werf, Paul E. R. Lipp...
DAC
2009
ACM
14 years 8 months ago
Quality-driven synthesis of embedded multi-mode control systems
At runtime, an embedded control system can switch between alternative functional modes. In each mode, the system operates by using a schedule and controllers that exploit the avai...
Soheil Samii, Petru Eles, Zebo Peng, Anton Cervin
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 6 days ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor