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PE
2006
Springer
103views Optimization» more  PE 2006»
13 years 7 months ago
The LCD interconnection of LRU caches and its analysis
In a multi-level cache such as those used for web caching, a hit at level l leads to the caching of the requested object in all intermediate caches on the reverse path (levels l -...
Nikolaos Laoutaris, Hao Che, Ioannis Stavrakakis
SPAA
2003
ACM
14 years 24 days ago
Throughput-centric routing algorithm design
The increasing application space of interconnection networks now encompasses several applications, such as packet routing and I/O interconnect, where the throughput of a routing a...
Brian Towles, William J. Dally, Stephen P. Boyd
ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 4 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
BMCBI
2006
123views more  BMCBI 2006»
13 years 7 months ago
Computational models with thermodynamic and composition features improve siRNA design
Background: Small interfering RNAs (siRNAs) have become an important tool in cell and molecular biology. Reliable design of siRNA molecules is essential for the needs of large fun...
Svetlana A. Shabalina, Alexey N. Spiridonov, Aleks...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 26 days ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...