731 search results - page 4 / 147 » Interconnect modeling for improved system-level design optim... |
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
ISPD
1997
ACM
13 years 11 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...