731 search results - page 82 / 147 » Interconnect modeling for improved system-level design optim... |
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
PVM
2009
Springer
14 years 3 months ago
2009
Springer
Abstract. Most parallel systems on which MPI is used are now hierarchical: some processors are much closer to others in terms of interconnect performance. One of the most common su...
MWCN
2004
Springer
14 years 2 months ago
2004
Springer
Inter-vehicle communication is becoming increasingly important in recent years. Traditional research efforts on vehicular networks have been put into safety or infotainment applica...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...