163 search results - page 15 / 33 » Interconnecting Computers: Architecture, Technology, and Eco... |
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
APCSAC
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...