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» Interconnection Networks for Scalable Quantum Computers
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VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 8 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
JSSPP
2004
Springer
14 years 1 months ago
Multi-toroidal Interconnects: Using Additional Communication Links to Improve Utilization of Parallel Computers
Three-dimensional torus is a common topology of network interconnects of multicomputers due to its simplicity and high scalability. A parallel job submitted to a three-dimensional...
Yariv Aridor, Tamar Domany, Oleg Goldshmidt, Edi S...
ICPP
2008
IEEE
14 years 2 months ago
Mapping Algorithms for Multiprocessor Tasks on Multi-Core Clusters
In this paper, we explore the use of hierarchically structured multiprocessor tasks (M-tasks) for programming multi-core cluster systems. These systems often have hierarchically s...
Jörg Dümmler, Thomas Rauber, Gudula R&uu...
ICPADS
1998
IEEE
13 years 11 months ago
Fault Tolerant All-to-All Broadcast in General Interconnection Networks
With respect to scalability and arbitrary topologies of the underlying networks in multiprogramming and multithread environment, fault tolerance in acknowledged ATAB and concurren...
Yuzhong Sun, Paul Y. S. Cheung, Xiaola Lin, Keqin ...
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
14 years 7 days ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner