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» Intermediate Performance of Rateless Codes
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ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
13 years 11 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
GLOBECOM
2009
IEEE
13 years 10 months ago
Dual-Hop Adaptive Packet Transmission with Regenerative Relaying for Wireless TDD Systems
We consider the design and performance analysis of adaptive modulation and coding (AMC) applied to regenerative dual-hop transmission systems, where a source node communicates with...
Andreas Muller, Hong-Chuan Yang
ASPLOS
2010
ACM
14 years 1 months ago
MacroSS: macro-SIMDization of streaming applications
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Ku...
SECON
2007
IEEE
14 years 1 months ago
OPERA: An Optimal Progressive Error Recovery Algorithm for Wireless Sensor Networks
—Wireless Sensor Networks (WSNs) require robustness against channel induced errors while retransmission based schemes prove too costly for energy constrained sensor nodes. Channe...
Saad B. Qaisar, Hayder Radha
VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
14 years 7 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...