108 search results - page 9 / 22 » Introspective 3D chips |
106
Voted
ASPDAC
2006
ACM
15 years 9 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
116
Voted
ISQED
2009
IEEE
15 years 10 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
112
Voted
GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
137
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CASES
2010
ACM
15 years 25 days ago
2010
ACM
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
140
Voted
GLVLSI
2006
IEEE
15 years 9 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...