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LCTRTS
2001
Springer
15 years 8 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
135
Voted
ISLPED
1996
ACM
91views Hardware» more  ISLPED 1996»
15 years 7 months ago
Energy minimization using multiple supply voltages
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling pro...
Jui-Ming Chang, Massoud Pedram
MICRO
1994
IEEE
81views Hardware» more  MICRO 1994»
15 years 7 months ago
Register file port requirements of transport triggered architectures
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
Jan Hoogerbrugge, Henk Corporaal
142
Voted
GECCO
2006
Springer
282views Optimization» more  GECCO 2006»
15 years 7 months ago
A genetic algorithm for the longest common subsequence problem
A genetic algorithm for the longest common subsequence problem encodes candidate sequences as binary strings that indicate subsequences of the shortest or first string. Its fitnes...
Brenda Hinkemeyer, Bryant A. Julstrom
124
Voted
COLING
1994
15 years 4 months ago
Two Parsing Algorithms by Means of Finite State Transducers
We present a new apl)roach , ilhlstrated by two algorithms> for parsing not only Finite SI.ate (:Iranlnlars but also Context Free Grainlnars and their extension, by means of fi...
Emmanuel Roche