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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 6 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
EURODAC
1994
IEEE
118views VHDL» more  EURODAC 1994»
15 years 6 months ago
A new knowledge-based design manager assistant for CAD frameworks
In this paper we introduce a new knowledgebased method for planning and managing the VLSI design process, based on prediction and advice, that minimizes search in a wide design sp...
Félix Moreno, Juan M. Meneses
EDOC
2007
IEEE
15 years 6 months ago
A Tool for Enterprise Architecture Analysis
Enterprise architecture advocates model-based decision-making on enterprise-wide information system issues. In order to provide decisionmaking support, enterprise architecture mode...
Pontus Johnson, Erik Johansson, Teodor Sommestad, ...
COMPSAC
2004
IEEE
15 years 6 months ago
Implementing Hierarchical Features in a Graphically Based Formal Modelling Language
Many developers who could benefit from building and analysing formal models of their systems are deterred from doing so by the process algebra style input languages of formal mode...
Peter Henderson, Robert John Walters, Stephen Crou...
103
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ESCIENCE
2006
IEEE
15 years 6 months ago
Running a Production Grid Site at the London e-Science Centre
This paper describes how the London e-Science Centre cluster MARS, a production 400+ Opteron CPU cluster, was integrated into the production Large Hadron Collider Compute Grid. It...
David McBride, Marko Krznaric, Olivier van der Aa,...