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» Issues of the Automatic Generation of HPF Loop Programs
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PLDI
2004
ACM
14 years 24 days ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
IEEEPACT
2009
IEEE
14 years 2 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 11 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
ICRA
2003
IEEE
110views Robotics» more  ICRA 2003»
14 years 20 days ago
Modelling of the human paralysed lower limb under FES
— The new generation of implanted neuroprostheses allows muscles to be controlled with fine accuracy, high selectivity and the repeatability of the muscle’s response can be ach...
David Guiraud, Philippe Poignet, Pierre-Brice Wieb...
CGO
2010
IEEE
14 years 2 months ago
Automatic creation of tile size selection models
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
Tomofumi Yuki, Lakshminarayanan Renganarayanan, Sa...