Sciweavers

682 search results - page 23 / 137
» Java Implementation Verification Using Reverse Engineering
Sort
View
SIGSOFT
2010
ACM
13 years 5 months ago
An effective dynamic analysis for detecting generalized deadlocks
We present an effective dynamic analysis for finding a broad class of deadlocks, including the well-studied lock-only deadlocks as well as the less-studied, but no less widespread...
Pallavi Joshi, Mayur Naik, Koushik Sen, David Gay
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
14 years 4 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
CODES
2005
IEEE
14 years 1 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
POPL
2007
ACM
14 years 7 months ago
Conditional must not aliasing for static race detection
Race detection algorithms for multi-threaded programs using the common lock-based synchronization idiom must correlate locks with the memory locations they guard. The heart of a p...
Mayur Naik, Alex Aiken
IEE
2008
115views more  IEE 2008»
13 years 7 months ago
Faithful mapping of model classes to mathematical structures
ion techniques are indispensable for the specification and verification of functional behavior of programs. In object-oriented ation languages like JML, a powerful abstraction tec...
Ádám Darvas, Peter Müller