Sciweavers

95 search results - page 17 / 19
» Jitter in Ring Oscillators
Sort
View
CCECE
2009
IEEE
14 years 1 months ago
A full-rate truly monolithic CMOS CDR for low-cost applications
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang...
ICCAD
2007
IEEE
131views Hardware» more  ICCAD 2007»
14 years 5 months ago
Low-overhead design technique for calibration of maximum frequency at multiple operating points
— Determination of maximum operating frequencies (Fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a Dynamic Voltage and Fr...
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid...
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 3 months ago
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
Sawal Ali, Li Ke, Reuben Wilcock, Peter Wilson
GLVLSI
2009
IEEE
92views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Online circuit reliability monitoring
In this work we propose an online reliability tracking framework that utilizes a hybrid network of on-chip temperature and delay sensors together with a circuit reliability macrom...
Bin Zhang
ARC
2010
Springer
178views Hardware» more  ARC 2010»
14 years 3 months ago
An Analysis of Delay Based PUF Implementations on FPGA
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabri...
Sergey Morozov, Abhranil Maiti, Patrick Schaumont