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MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
14 years 2 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
INFOCOM
2000
IEEE
13 years 12 months ago
Egress Admission Control
—Allocating resources for multimedia traffic flows with real-time performance requirements is an important challenge for future packet networks. However, in large-scale networks,...
Coskun Cetinkaya, Edward W. Knightly
CGO
2004
IEEE
13 years 11 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
13 years 11 months ago
A Framework for Battery-Aware Sensor Management
A distributed sensor network (DSN) designed to cover a given region R, is said to be alive if there is at least one subset of sensors that can collectively cover (sense) the regio...
Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chop...
ICA
2010
Springer
13 years 8 months ago
Recovering Spikes from Noisy Neuronal Calcium Signals via Structured Sparse Approximation
Two-photon calcium imaging is an emerging experimental technique that enables the study of information processing within neural circuits in vivo. While the spatial resolution of th...
Eva L. Dyer, Marco F. Duarte, Don H. Johnson, Rich...